/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

/*
 * nthw_fpga_reg_defs_spim.h
 *
 * Auto-generated file - do *NOT* edit
 *
 */

#ifndef _NTHW_FPGA_REG_DEFS_SPIM_
#define _NTHW_FPGA_REG_DEFS_SPIM_

/* SPIM */
#define NTHW_MOD_SPIM (0x1da437bfUL)
#define SPIM_CFG (0x90b6b0d5UL)
#define SPIM_CFG_PRE (0x156a8ea9UL)
#define SPIM_CFG_CLK (0xeb7046a1UL)
#define SPIM_CFG_CLK_MODE (0x228be0cbUL)
#define SPIM_CMD (0xea4b38a4UL)
#define SPIM_CMD_ADDR (0x95fe56baUL)
#define SPIM_CMD_CMD (0x9c30279bUL)
#define SPIM_CMD_DATA (0x6a9737ecUL)
#define SPIM_CONF0 (0x84d4acb5UL)
#define SPIM_CONF0_BYTE_PACE (0xc9a95016UL)
#define SPIM_CONF0_MIRROR_EN (0xa710688UL)
#define SPIM_CONF0_MSB_FIRST (0x5f60c96aUL)
#define SPIM_CONF0_PRESCAL_CLK (0xadb38a7UL)
#define SPIM_CONF0_RESTART (0x1fda85dcUL)
#define SPIM_CONF0_RST (0x64e3b3bUL)
#define SPIM_CONF0_SYNC_MON_EN (0x591a639eUL)
#define SPIM_CONF1 (0xf3d39c23UL)
#define SPIM_CONF1_MIRROR_PACE (0x370f3f34UL)
#define SPIM_CONF1_MIRROR_SCAN (0x83daffbeUL)
#define SPIM_CONF1_SYNCTIMEOUT (0x1b5d30cdUL)
#define SPIM_CONF2 (0x6adacd99UL)
#define SPIM_CONF2_MIRROR_PRESC (0x3a8c10e2UL)
#define SPIM_CONF2_OPCODE_RD (0x3eb6084fUL)
#define SPIM_CONF2_OPCODE_WR (0xb715495bUL)
#define SPIM_CONF3 (0x1dddfd0fUL)
#define SPIM_CONF3_MIRROR_RDADR (0xc00ba60fUL)
#define SPIM_CONF3_MIRROR_WRADR (0x7d99213cUL)
#define SPIM_CR (0x1c1de013UL)
#define SPIM_CR_EN (0xf2e0e72fUL)
#define SPIM_CR_LOOP (0xdeb882aUL)
#define SPIM_CR_RXRST (0x487f7d1bUL)
#define SPIM_CR_TXRST (0xc73f88bbUL)
#define SPIM_DRR (0xd68a95eeUL)
#define SPIM_DRR_DRR (0x78766633UL)
#define SPIM_DTR (0x80d03268UL)
#define SPIM_DTR_DTR (0xf87522a8UL)
#define SPIM_REPLY (0x6ed04defUL)
#define SPIM_REPLY_RDDATA (0x40db3b24UL)
#define SPIM_SR (0x56dff242UL)
#define SPIM_SR_DONE (0xdb47e9a1UL)
#define SPIM_SR_RXEMPTY (0x489aaf91UL)
#define SPIM_SR_RXFULL (0xd26832f5UL)
#define SPIM_SR_RXLVL (0x4c67ae59UL)
#define SPIM_SR_TXEMPTY (0x2b4a9aabUL)
#define SPIM_SR_TXFULL (0x431d1e8UL)
#define SPIM_SR_TXLVL (0xc3275bf9UL)
#define SPIM_SRR (0xcfe3201bUL)
#define SPIM_SRR_RST (0x32dc8fc5UL)
#define SPIM_STATUS (0xd04220ceUL)
#define SPIM_STATUS_CMDPENDING (0x74ed833fUL)
#define SPIM_STATUS_RESERVED (0xa50278bUL)
#define SPIM_STATUS_RESYNCDETECT (0x5b268881UL)
#define SPIM_STATUS_RESYNCING (0x5ec3f11UL)

#endif	/* _NTHW_FPGA_REG_DEFS_SPIM_ */

/*
 * Auto-generated file - do *NOT* edit
 */
