/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

/*
 * nthw_fpga_reg_defs_rmc.h
 *
 * Auto-generated file - do *NOT* edit
 *
 */

#ifndef _NTHW_FPGA_REG_DEFS_RMC_
#define _NTHW_FPGA_REG_DEFS_RMC_

/* RMC */
#define NTHW_MOD_RMC (0x236444eUL)
#define RMC_CTRL (0x4c45f748UL)
#define RMC_CTRL_BLOCK_KEEPA (0x5e036c8UL)
#define RMC_CTRL_BLOCK_MAC_PORT (0x582a6486UL)
#define RMC_CTRL_BLOCK_RPP_SLICE (0x58c719cUL)
#define RMC_CTRL_BLOCK_STATT (0xb36d5342UL)
#define RMC_CTRL_LAG_PHY_ODD_EVEN (0xf4613c9UL)
#define RMC_DBG (0x578721f2UL)
#define RMC_DBG_MERGE (0xebfd6f00UL)
#define RMC_MAC_IF (0x806bb8b0UL)
#define RMC_MAC_IF_ERR (0xa79e974aUL)
#define RMC_STATUS (0x3c415d75UL)
#define RMC_STATUS_DESCR_FIFO_OF (0x7be968baUL)
#define RMC_STATUS_SF_RAM_OF (0x1832173dUL)

#endif	/* _NTHW_FPGA_REG_DEFS_RMC_ */

/*
 * Auto-generated file - do *NOT* edit
 */
