/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

/*
 * nthw_fpga_reg_defs_rst9574.h
 *
 * Auto-generated file - do *NOT* edit
 *
 */

#ifndef _NTHW_FPGA_REG_DEFS_RST9574_
#define _NTHW_FPGA_REG_DEFS_RST9574_

/* RST9574 */
#define NTHW_MOD_RST9574 (0xbf22c9ffUL)
#define RST9574_LATCH (0x3ed1e303UL)
#define RST9574_LATCH_DDR4_CALIB_COMPLETE (0x3b59afedUL)
#define RST9574_LATCH_PHY_FTILE_RDY (0x4e701f0fUL)
#define RST9574_LATCH_PHY_FTILE_RST_DONE (0xd55b1659UL)
#define RST9574_RST (0x4f1625b6UL)
#define RST9574_RST_DDR4 (0x152e69ddUL)
#define RST9574_RST_PHY_FTILE (0x8455e296UL)
#define RST9574_RST_SYS (0x6a2c0d30UL)
#define RST9574_STAT (0x160fed08UL)
#define RST9574_STAT_DDR4_CALIB_COMPLETE (0x768d8717UL)
#define RST9574_STAT_PHY_FTILE_RDY (0x727ca032UL)
#define RST9574_STAT_PHY_FTILE_RST_DONE (0xb312b439UL)

#endif	/* _NTHW_FPGA_REG_DEFS_RST9574_ */

/*
 * Auto-generated file - do *NOT* edit
 */
