/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

/*
 * nthw_fpga_reg_defs_phy_tile.h
 *
 * Auto-generated file - do *NOT* edit
 *
 */

#ifndef _NTHW_FPGA_REG_DEFS_PHY_TILE_
#define _NTHW_FPGA_REG_DEFS_PHY_TILE_

/* PHY_TILE */
#define NTHW_MOD_PHY_TILE (0x4e0aef6eUL)
#define PHY_TILE_DR_CFG (0x763df0f3UL)
#define PHY_TILE_DR_CFG_DYN_RST (0x2ff2174cUL)
#define PHY_TILE_DR_CFG_FEATURES (0xf43413f2UL)
#define PHY_TILE_DR_CFG_SCRATCH (0x605efc72UL)
#define PHY_TILE_DR_CFG_TX_FLUSH_LEVEL (0x528b497bUL)
#define PHY_TILE_DR_CFG_STATUS (0x252aff33UL)
#define PHY_TILE_DR_CFG_STATUS_CURR_PROFILE_ID (0x98db7e13UL)
#define PHY_TILE_DR_CFG_STATUS_ERROR (0x594c35e7UL)
#define PHY_TILE_DR_CFG_STATUS_IN_PROGRESS (0x62cdc29fUL)
#define PHY_TILE_DYN_RECONFIG_BASE (0xda7abd93UL)
#define PHY_TILE_DYN_RECONFIG_BASE_BUSY (0x3b97f6c6UL)
#define PHY_TILE_DYN_RECONFIG_BASE_CMD (0xf6b609f6UL)
#define PHY_TILE_DYN_RECONFIG_BASE_PTR (0x87020896UL)
#define PHY_TILE_DYN_RECONFIG_DATA (0xb73db091UL)
#define PHY_TILE_DYN_RECONFIG_DATA_DATA (0x74d2a935UL)
#define PHY_TILE_LINK_SUMMARY_0 (0x2e6c2bb2UL)
#define PHY_TILE_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT (0x658fa4f2UL)
#define PHY_TILE_LINK_SUMMARY_0_LH_REMOTE_FAULT (0x12c794faUL)
#define PHY_TILE_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE (0x99e0ad8bUL)
#define PHY_TILE_LINK_SUMMARY_0_LINK_DOWN_CNT (0x7c6a63a9UL)
#define PHY_TILE_LINK_SUMMARY_0_LL_PHY_LINK_STATE (0x694563dcUL)
#define PHY_TILE_LINK_SUMMARY_0_LL_RX_AM_LOCK (0xc958731bUL)
#define PHY_TILE_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK (0x1ae5c634UL)
#define PHY_TILE_LINK_SUMMARY_0_NT_PHY_LINK_STATE (0x284d52caUL)
#define PHY_TILE_LINK_SUMMARY_1 (0x596b1b24UL)
#define PHY_TILE_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT (0xc00434fcUL)
#define PHY_TILE_LINK_SUMMARY_1_LH_REMOTE_FAULT (0x95615fb9UL)
#define PHY_TILE_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE (0xf76cb6caUL)
#define PHY_TILE_LINK_SUMMARY_1_LINK_DOWN_CNT (0xc591b841UL)
#define PHY_TILE_LINK_SUMMARY_1_LL_PHY_LINK_STATE (0xbea7e384UL)
#define PHY_TILE_LINK_SUMMARY_1_LL_RX_AM_LOCK (0x70a3a8f3UL)
#define PHY_TILE_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK (0xf5b770d5UL)
#define PHY_TILE_LINK_SUMMARY_1_NT_PHY_LINK_STATE (0xffafd292UL)
#define PHY_TILE_PORT_0_ETH_0_BASE (0x337c4712UL)
#define PHY_TILE_PORT_0_ETH_0_BASE_BUSY (0xd5fbad30UL)
#define PHY_TILE_PORT_0_ETH_0_BASE_CMD (0x948cd3f4UL)
#define PHY_TILE_PORT_0_ETH_0_BASE_PTR (0xe538d294UL)
#define PHY_TILE_PORT_0_ETH_0_DATA (0x5e3b4a10UL)
#define PHY_TILE_PORT_0_ETH_0_DATA_DATA (0x9abef2c3UL)
#define PHY_TILE_PORT_0_XCVR_0_BASE (0x758a7765UL)
#define PHY_TILE_PORT_0_XCVR_0_BASE_BUSY (0x79488eafUL)
#define PHY_TILE_PORT_0_XCVR_0_BASE_CMD (0x9b560cdfUL)
#define PHY_TILE_PORT_0_XCVR_0_BASE_PTR (0xeae20dbfUL)
#define PHY_TILE_PORT_0_XCVR_0_DATA (0x18cd7a67UL)
#define PHY_TILE_PORT_0_XCVR_0_DATA_DATA (0x360dd15cUL)
#define PHY_TILE_PORT_0_XCVR_1_BASE (0xbed6a4c0UL)
#define PHY_TILE_PORT_0_XCVR_1_BASE_BUSY (0xb8c6516fUL)
#define PHY_TILE_PORT_0_XCVR_1_BASE_CMD (0x749467e1UL)
#define PHY_TILE_PORT_0_XCVR_1_BASE_PTR (0x5206681UL)
#define PHY_TILE_PORT_0_XCVR_1_DATA (0xd391a9c2UL)
#define PHY_TILE_PORT_0_XCVR_1_DATA_DATA (0xf7830e9cUL)
#define PHY_TILE_PORT_0_XCVR_2_BASE (0x3842d66eUL)
#define PHY_TILE_PORT_0_XCVR_2_BASE_BUSY (0x2124376eUL)
#define PHY_TILE_PORT_0_XCVR_2_BASE_CMD (0x9fa3dce2UL)
#define PHY_TILE_PORT_0_XCVR_2_BASE_PTR (0xee17dd82UL)
#define PHY_TILE_PORT_0_XCVR_2_DATA (0x5505db6cUL)
#define PHY_TILE_PORT_0_XCVR_2_DATA_DATA (0x6e61689dUL)
#define PHY_TILE_PORT_0_XCVR_3_BASE (0xf31e05cbUL)
#define PHY_TILE_PORT_0_XCVR_3_BASE_BUSY (0xe0aae8aeUL)
#define PHY_TILE_PORT_0_XCVR_3_BASE_CMD (0x7061b7dcUL)
#define PHY_TILE_PORT_0_XCVR_3_BASE_PTR (0x1d5b6bcUL)
#define PHY_TILE_PORT_0_XCVR_3_DATA (0x9e5908c9UL)
#define PHY_TILE_PORT_0_XCVR_3_DATA_DATA (0xafefb75dUL)
#define PHY_TILE_PORT_1_ETH_0_BASE (0xa8d90b7dUL)
#define PHY_TILE_PORT_1_ETH_0_BASE_BUSY (0x525d6673UL)
#define PHY_TILE_PORT_1_ETH_0_BASE_CMD (0x3ae44265UL)
#define PHY_TILE_PORT_1_ETH_0_BASE_PTR (0x4b504305UL)
#define PHY_TILE_PORT_1_ETH_0_DATA (0xc59e067fUL)
#define PHY_TILE_PORT_1_ETH_0_DATA_DATA (0x1d183980UL)
#define PHY_TILE_PORT_1_XCVR_0_BASE (0xa81caee0UL)
#define PHY_TILE_PORT_1_XCVR_0_BASE_BUSY (0x961a384eUL)
#define PHY_TILE_PORT_1_XCVR_0_BASE_CMD (0x1cf0c79cUL)
#define PHY_TILE_PORT_1_XCVR_0_BASE_PTR (0x6d44c6fcUL)
#define PHY_TILE_PORT_1_XCVR_0_DATA (0xc55ba3e2UL)
#define PHY_TILE_PORT_1_XCVR_0_DATA_DATA (0xd95f67bdUL)
#define PHY_TILE_PORT_1_XCVR_1_BASE (0x63407d45UL)
#define PHY_TILE_PORT_1_XCVR_1_BASE_BUSY (0x5794e78eUL)
#define PHY_TILE_PORT_1_XCVR_1_BASE_CMD (0xf332aca2UL)
#define PHY_TILE_PORT_1_XCVR_1_BASE_PTR (0x8286adc2UL)
#define PHY_TILE_PORT_1_XCVR_1_DATA (0xe077047UL)
#define PHY_TILE_PORT_1_XCVR_1_DATA_DATA (0x18d1b87dUL)
#define PHY_TILE_PORT_1_XCVR_2_BASE (0xe5d40febUL)
#define PHY_TILE_PORT_1_XCVR_2_BASE_BUSY (0xce76818fUL)
#define PHY_TILE_PORT_1_XCVR_2_BASE_CMD (0x180517a1UL)
#define PHY_TILE_PORT_1_XCVR_2_BASE_PTR (0x69b116c1UL)
#define PHY_TILE_PORT_1_XCVR_2_DATA (0x889302e9UL)
#define PHY_TILE_PORT_1_XCVR_2_DATA_DATA (0x8133de7cUL)
#define PHY_TILE_PORT_1_XCVR_3_BASE (0x2e88dc4eUL)
#define PHY_TILE_PORT_1_XCVR_3_BASE_BUSY (0xff85e4fUL)
#define PHY_TILE_PORT_1_XCVR_3_BASE_CMD (0xf7c77c9fUL)
#define PHY_TILE_PORT_1_XCVR_3_BASE_PTR (0x86737dffUL)
#define PHY_TILE_PORT_1_XCVR_3_DATA (0x43cfd14cUL)
#define PHY_TILE_PORT_1_XCVR_3_DATA_DATA (0x40bd01bcUL)
#define PHY_TILE_PORT_COMP_0 (0xfc048a04UL)
#define PHY_TILE_PORT_COMP_0_RX_COMPENSATION (0xffba9733UL)
#define PHY_TILE_PORT_COMP_0_TX_COMPENSATION (0xdd4043c1UL)
#define PHY_TILE_PORT_COMP_1 (0x8b03ba92UL)
#define PHY_TILE_PORT_COMP_1_RX_COMPENSATION (0x781c5c70UL)
#define PHY_TILE_PORT_COMP_1_TX_COMPENSATION (0x5ae68882UL)
#define PHY_TILE_PORT_CONFIG (0x24e3ab60UL)
#define PHY_TILE_PORT_CONFIG_DYN_RESET (0x72b5f859UL)
#define PHY_TILE_PORT_CONFIG_NT_FORCE_LINK_DOWN_0 (0x7e66781UL)
#define PHY_TILE_PORT_CONFIG_NT_FORCE_LINK_DOWN_1 (0x70e15717UL)
#define PHY_TILE_PORT_CONFIG_NT_LINKUP_LATENCY_0 (0x33fd94c2UL)
#define PHY_TILE_PORT_CONFIG_NT_LINKUP_LATENCY_1 (0x44faa454UL)
#define PHY_TILE_PORT_CONFIG_RESET_0 (0xf0e1e1c4UL)
#define PHY_TILE_PORT_CONFIG_RESET_1 (0x87e6d152UL)
#define PHY_TILE_PORT_CONFIG_RX_RESET_0 (0x70027edeUL)
#define PHY_TILE_PORT_CONFIG_RX_RESET_1 (0x7054e48UL)
#define PHY_TILE_PORT_CONFIG_TX_RESET_0 (0x7d1c0e99UL)
#define PHY_TILE_PORT_CONFIG_TX_RESET_1 (0xa1b3e0fUL)
#define PHY_TILE_PORT_CONFIG_0 (0x7eda56ecUL)
#define PHY_TILE_PORT_CONFIG_0_NT_AUTO_FORCE_LINK_DOWN (0x1e02d057UL)
#define PHY_TILE_PORT_CONFIG_0_NT_FORCE_LINK_DOWN (0xf21d946dUL)
#define PHY_TILE_PORT_CONFIG_0_NT_LINKUP_LATENCY (0x833ea2b3UL)
#define PHY_TILE_PORT_CONFIG_0_RST (0xcbf3bb99UL)
#define PHY_TILE_PORT_CONFIG_0_RX_RST (0x1c7f59c7UL)
#define PHY_TILE_PORT_CONFIG_0_TX_RST (0xca26badaUL)
#define PHY_TILE_PORT_CONFIG_1 (0x9dd667aUL)
#define PHY_TILE_PORT_CONFIG_1_NT_AUTO_FORCE_LINK_DOWN (0xbb894059UL)
#define PHY_TILE_PORT_CONFIG_1_NT_FORCE_LINK_DOWN (0x977aaf2bUL)
#define PHY_TILE_PORT_CONFIG_1_NT_LINKUP_LATENCY (0x54dc22ebUL)
#define PHY_TILE_PORT_CONFIG_1_RST (0xf6939229UL)
#define PHY_TILE_PORT_CONFIG_1_RX_RST (0xd0d55959UL)
#define PHY_TILE_PORT_CONFIG_1_TX_RST (0x68cba44UL)
#define PHY_TILE_PORT_STATUS (0x8b69e100UL)
#define PHY_TILE_PORT_STATUS_RESET_ACK_N_0 (0x812f344UL)
#define PHY_TILE_PORT_STATUS_RESET_ACK_N_1 (0x7f15c3d2UL)
#define PHY_TILE_PORT_STATUS_RX_AM_LOCK_0 (0x18c38950UL)
#define PHY_TILE_PORT_STATUS_RX_AM_LOCK_1 (0x6fc4b9c6UL)
#define PHY_TILE_PORT_STATUS_RX_BLOCK_LOCK_0 (0x72b847a5UL)
#define PHY_TILE_PORT_STATUS_RX_BLOCK_LOCK_1 (0x5bf7733UL)
#define PHY_TILE_PORT_STATUS_RX_CDR_LOCK_0 (0x8557733cUL)
#define PHY_TILE_PORT_STATUS_RX_CDR_LOCK_1 (0xf25043aaUL)
#define PHY_TILE_PORT_STATUS_RX_HI_BER_0 (0xae6e5427UL)
#define PHY_TILE_PORT_STATUS_RX_HI_BER_1 (0xd96964b1UL)
#define PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_0 (0xb7de3d5eUL)
#define PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_1 (0xc0d90dc8UL)
#define PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_0 (0x690e7dbcUL)
#define PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_1 (0x1e094d2aUL)
#define PHY_TILE_PORT_STATUS_RX_PCS_READY_0 (0x4bb3d53cUL)
#define PHY_TILE_PORT_STATUS_RX_PCS_READY_1 (0x3cb4e5aaUL)
#define PHY_TILE_PORT_STATUS_RX_PTP_OFFSET_DATA_VALID_0 (0x4a8305e7UL)
#define PHY_TILE_PORT_STATUS_RX_PTP_OFFSET_DATA_VALID_1 (0x3d843571UL)
#define PHY_TILE_PORT_STATUS_RX_PTP_READY_0 (0xb74c7368UL)
#define PHY_TILE_PORT_STATUS_RX_PTP_READY_1 (0xc04b43feUL)
#define PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_0 (0x7160c5c7UL)
#define PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_1 (0x667f551UL)
#define PHY_TILE_PORT_STATUS_SYSTEMPLL_LOCK (0x3d44b5b8UL)
#define PHY_TILE_PORT_STATUS_SYS_PLL_LOCKED_0 (0x9a284858UL)
#define PHY_TILE_PORT_STATUS_SYS_PLL_LOCKED_1 (0xed2f78ceUL)
#define PHY_TILE_PORT_STATUS_TX_LANES_STABLE_0 (0x9d0d322aUL)
#define PHY_TILE_PORT_STATUS_TX_LANES_STABLE_1 (0xea0a02bcUL)
#define PHY_TILE_PORT_STATUS_TX_PLL_LOCKED_0 (0x56587371UL)
#define PHY_TILE_PORT_STATUS_TX_PLL_LOCKED_1 (0x215f43e7UL)
#define PHY_TILE_PORT_STATUS_0 (0x8d2e3a4fUL)
#define PHY_TILE_PORT_STATUS_0_RESET_ACK_N (0xa0728651UL)
#define PHY_TILE_PORT_STATUS_0_RX_AM_LOCK (0x84cbe16dUL)
#define PHY_TILE_PORT_STATUS_0_RX_HI_BER (0x3284d104UL)
#define PHY_TILE_PORT_STATUS_0_RX_LOCAL_FAULT (0x581a604cUL)
#define PHY_TILE_PORT_STATUS_0_RX_PCS_FULLY_ALIGNED (0x8a9f2523UL)
#define PHY_TILE_PORT_STATUS_0_RX_REMOTE_FAULT (0xa42546cfUL)
#define PHY_TILE_PORT_STATUS_0_RX_RESET_ACK_N (0x5d1fa363UL)
#define PHY_TILE_PORT_STATUS_0_SYS_PLL_LOCKED (0x1624ce5aUL)
#define PHY_TILE_PORT_STATUS_0_TX_LANES_STABLE (0x7a66b5c7UL)
#define PHY_TILE_PORT_STATUS_0_TX_PLL_LOCKED (0x29cd220bUL)
#define PHY_TILE_PORT_STATUS_0_TX_RESET_ACK_N (0xa5dde8d5UL)
#define PHY_TILE_PORT_STATUS_1 (0xfa290ad9UL)
#define PHY_TILE_PORT_STATUS_1_RESET_ACK_N (0x7de45fd4UL)
#define PHY_TILE_PORT_STATUS_1_RX_AM_LOCK (0x1f6ead02UL)
#define PHY_TILE_PORT_STATUS_1_RX_HI_BER (0xf30a0ec4UL)
#define PHY_TILE_PORT_STATUS_1_RX_LOCAL_FAULT (0xf672f1ddUL)
#define PHY_TILE_PORT_STATUS_1_RX_PCS_FULLY_ALIGNED (0x9db741e3UL)
#define PHY_TILE_PORT_STATUS_1_RX_REMOTE_FAULT (0x23838d8cUL)
#define PHY_TILE_PORT_STATUS_1_RX_RESET_ACK_N (0xf37732f2UL)
#define PHY_TILE_PORT_STATUS_1_SYS_PLL_LOCKED (0xb84c5fcbUL)
#define PHY_TILE_PORT_STATUS_1_TX_LANES_STABLE (0xfdc07e84UL)
#define PHY_TILE_PORT_STATUS_1_TX_PLL_LOCKED (0x9036f9e3UL)
#define PHY_TILE_PORT_STATUS_1_TX_RESET_ACK_N (0xbb57944UL)
#define PHY_TILE_SCRATCH (0xcd637527UL)
#define PHY_TILE_SCRATCH_DATA (0x1934d873UL)
#define PHY_TILE_SYS_PLL (0x65742dccUL)
#define PHY_TILE_SYS_PLL_DISABLE_REFCLK_MONITOR (0xf740e941UL)
#define PHY_TILE_SYS_PLL_EN_REFCLK_FGT (0x8f5bac3aUL)
#define PHY_TILE_SYS_PLL_FORCE_RST (0xa3d1af1fUL)
#define PHY_TILE_SYS_PLL_FORWARD_RST (0x26a13387UL)
#define PHY_TILE_SYS_PLL_GET_RDY (0xa2822d9bUL)
#define PHY_TILE_SYS_PLL_REFCLK_FGT_ENABLED (0x57072ab1UL)
#define PHY_TILE_SYS_PLL_SET_RDY (0x31139546UL)
#define PHY_TILE_SYS_PLL_SYSTEMPLL_LOCK (0x467d08f6UL)

#endif	/* _NTHW_FPGA_REG_DEFS_PHY_TILE_ */

/*
 * Auto-generated file - do *NOT* edit
 */
