/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

/*
 * nthw_fpga_reg_defs_spis.h
 *
 * Auto-generated file - do *NOT* edit
 *
 */

#ifndef _NTHW_FPGA_REG_DEFS_SPIS_
#define _NTHW_FPGA_REG_DEFS_SPIS_

/* SPIS */
#define NTHW_MOD_SPIS (0xe7ab0adcUL)
#define SPIS_CR (0xacdbc0bfUL)
#define SPIS_CR_DEBUG (0xf2096408UL)
#define SPIS_CR_EN (0xc50100bcUL)
#define SPIS_CR_LOOP (0x69e911c9UL)
#define SPIS_CR_RXRST (0x7118cc40UL)
#define SPIS_CR_TXRST (0xfe5839e0UL)
#define SPIS_DRR (0x95abc0dUL)
#define SPIS_DRR_DRR (0x1c74ffd0UL)
#define SPIS_DTR (0x5f001b8bUL)
#define SPIS_DTR_DTR (0x9c77bb4bUL)
#define SPIS_RAM_CTRL (0x682dc7d8UL)
#define SPIS_RAM_CTRL_ADR (0x15c2f809UL)
#define SPIS_RAM_CTRL_CNT (0x5ca61d8UL)
#define SPIS_RAM_DATA (0xc7fc45c1UL)
#define SPIS_RAM_DATA_DATA (0x422b05eaUL)
#define SPIS_SR (0xe619d2eeUL)
#define SPIS_SR_DONE (0xbf457042UL)
#define SPIS_SR_FRAME_ERR (0x31b5d7e4UL)
#define SPIS_SR_READ_ERR (0xa83d91f1UL)
#define SPIS_SR_RXEMPTY (0xadb39173UL)
#define SPIS_SR_RXFULL (0x2ee8dd38UL)
#define SPIS_SR_RXLVL (0x75001f02UL)
#define SPIS_SR_TXEMPTY (0xce63a449UL)
#define SPIS_SR_TXFULL (0xf8b13e25UL)
#define SPIS_SR_TXLVL (0xfa40eaa2UL)
#define SPIS_SR_WRITE_ERR (0x9d389ce2UL)
#define SPIS_SRR (0x103309f8UL)
#define SPIS_SRR_RST (0x56de1626UL)

#endif	/* _NTHW_FPGA_REG_DEFS_SPIS_ */

/*
 * Auto-generated file - do *NOT* edit
 */
